
W skrócie
zdania wybrane z oferty- We are looking for an experienced Verification Engineer with approximately 5 years of hands-on experience to own block and subsystem-level functional verification.
- In this role, you will build and enhance UVM-based testbenches, execute coverage-driven verification, and collaborate closely with RTL design teams to ensure high silicon quality.
- Develop, maintain, and execute UVM-based verification environments, testbenches, scoreboards, and reusable VIPs.
Technologie
Pełny opis
z pracuj.plTechnologies we use
Expected
- SystemVerilog
- UVM
- ASIC
- SoC
- RTL
- AXI
- AHB
- APB
- PCIe
- Ethernet
- Cadence Xcelium
- Synopsys VCS
- Siemens Questa
- DVE
- Verdi
- Python
- Perl
- Bash
About the project
We are looking for an experienced Verification Engineer with approximately 5 years of hands-on experience to own block and subsystem-level functional verification. In this role, you will build and enhance UVM-based testbenches, execute coverage-driven verification, and collaborate closely with RTL design teams to ensure high silicon quality.
Your responsibilities
- Develop, maintain, and execute UVM-based verification environments, testbenches, scoreboards, and reusable VIPs.
- Define and implement comprehensive verification plans based on architecture and design specifications.
- Construct functional coverage models, analyze code coverage, and drive coverage closure.
- Write SystemVerilog for protocol checking and interface verification.
- Perform root-cause debugging of complex hardware issues at both RTL and gate-level simulations.
- Collaborate with design and architecture teams to resolve bugs and refine feature specifications.
- Automate regression suites, test execution, and result tracking using scripting tools.
Our requirements
- Education: B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
- Experience: ~5 years of proven experience in ASIC/SoC digital functional verification.
- Core Expertise:
- Advanced proficiency in SystemVerilog and UVM.
- Strong hands-on experience building UVM testbenches from scratch or extending existing frameworks.
- Solid understanding of standard bus protocols (e.g., AXI, AHB, APB, PCIe, or Ethernet).
- Hands-on experience with industry-standard EDA simulation and debug tools (Cadence Xcelium, Synopsys VCS, Siemens Questa, DVE/Verdi).
- Proficiency in scripting languages (Python, Perl, or Bash) for verification automation.
- Soft Skills: Excellent problem-solving abilities, strong communication skills, and a collaborative team mindset.
Benefits
- sharing the costs of sports activities
- private medical care
- sharing the costs of foreign language classes
- fruits
- integration events
- corporate gym
- coffee / tea
- drinks
- birthday celebration
- employee referral program
Recruitment stages
- Rozmowa telefoniczna – wstępna rozmowa z Rekruterem
- Rozmowa kwalifikacyjna – spotkanie z przedstawicielem firmy
Integral Solutions
Integral Solutions, Informatica Platinum Partner Enterprise, od ponad 20 lat dostarcza nowoczesne rozwiązania IT dla biznesu, oferując usługi m.in. w zakresie integracji danych, Data Engineering (Big Data) oraz Data Governance. Specjalizując się w rekrutacji pracowników z branży IT, nie tylko w obszarze danych, pomaga Klientom powiększać zespoły projektowe o profesjonalistów IT.
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Historia oferty
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